Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

P. Sakian; M. Saffari; M. Atarodi; A. Tajalli

Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

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Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

Author(s): P. Sakian ; M. Saffari ; M. Atarodi ; A. Tajalli
DOI: 10.1049/iet-cds:20080111

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Author(s): P. Sakian ¹ ; M. Saffari ¹ ; M. Atarodi ¹ ; A. Tajalli ^{1, 2}
- Affiliations: 1: Electrical Engineering Department, Sharif University of Technology, Tehran, Iran
  2: Microelectronic Systems Lab. (LSM), Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
Source: Volume 2, Issue 5, October 2008, p. 409 – 421
DOI: 10.1049/iet-cds:20080111 , Print ISSN 1751-858X, Online ISSN 1751-8598

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A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 µm CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW.

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Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance

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