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High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

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Published

A high-speed VLSI implementation of a 233-bit serial-in parallel-out finite field multiplier is presented. The proposed design performs multiplication using a reordered normal basis; a permutation of a type II optimal normal basis. The multiplier was realised in a 0.18-µm CMOS technology using multiples of a domino logic block. The multiplier was simulated, and functioned correctly up to a clock rate of 1.587 GHz, achieving greater performance while occupying less area compared to similar designs. The presented design methodology can also be used for other finite field multipliers possessing regular architectures. This multiplier's size of 233 bits is currently recommended by the National Institute of Standards and Technology (NIST) in their elliptic curve digital signature standard (ECDSS), and is used in practice for binary field multiplication in Elliptic Curve Cryptography (ECC).

Inspec keywords: multiplying circuits; VLSI

Other keywords: CMOS technology; elliptic curve digital signature standard; high speed VLSI; binary field multiplication; domino logic block; serial-in parallel-out finite field multiplier; finite field multipliers; elliptic curve cryptography; high speed hardware; reordered normal basis

Subjects: Logic and switching circuits; Logic circuits; Semiconductor integrated circuit design, layout, modelling and testing

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