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SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations

SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations

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  • Author(s): Z. Feng 1 ; P. Li 1 ; Z. Ren 2
    • View affiliations
    • Affiliations: 1: Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, USA
      2: Department of Electrical and Computer Engineering, Mentor Graphics Corp., San Jose, USA
  • Source: Volume 3, Issue 5, October 2009, p. 248 – 258
    DOI:  10.1049/iet-cds.2009.0040 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Published

While traditional worst-case corner analysis is often too pessimistic for nanometer designs, full-blown statistical circuit analysis requires significant modelling infrastructures. In this study, a design-dependent statistical interconnect corner extraction (SICE) methodology is proposed. SICE achieves a good trade-off between complexity and pessimism by extracting more than one process corners in a statistical sense, which are also design dependent. Our new approach removes the pessimism incurred in prior work while being computationally efficient. The efficiency of SICE comes from the use of parameter dimension reduction techniques. The statistical corners are further compacted by an iterative output clustering method. Numerical results show that SICE achieves up to 260X speedups over the Monte Carlo method.

Inspec keywords: iterative methods; integrated circuit design; CMOS integrated circuits; integrated circuit interconnections; statistical analysis

Other keywords: SICE methodology; design-dependent statistical interconnect corner extraction; CMOS technologies; full-blown statistical circuit analysis; traditional worst-case corner analysis; iterative output clustering method; intra-die variation; interconnect delay variations; inter-die variation; parameter dimension reduction technique

Subjects: Other topics in statistics; Metallisation and interconnection technology; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Interpolation and function approximation (numerical analysis)

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