Low-power programmable divider with a shared counter for frequency synthesiser

K.-Y. Kim; Y.-J. Min; S.-W. Kim; J. Park

Low-power programmable divider with a shared counter for frequency synthesiser

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Low-power programmable divider with a shared counter for frequency synthesiser

Author(s): K.-Y. Kim ; Y.-J. Min ; S.-W. Kim ; J. Park
DOI: 10.1049/iet-cds.2010.0120

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Author(s): K.-Y. Kim ¹ ; Y.-J. Min ¹ ; S.-W. Kim ¹ ; J. Park ¹
- Affiliations: 1: School of Electrical Engineering, Korea University, Seoul, Republic of Korea
Source: Volume 5, Issue 3, May 2011, p. 170 – 176
DOI: 10.1049/iet-cds.2010.0120 , Print ISSN 1751-858X, Online ISSN 1751-8598

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A low-power programmable divider (PD) for frequency synthesiser is presented in this study. Instead of two counters used in conventional PD, a shared counter with a small control circuit is exploited in order to reduce the output load capacitance and the redundant counter operations in the divider. A novel glitchless D flip-flop is also proposed by considering the switching activities of the internal nodes of the flip-flop. The authors' proposed PD was fabricated in a standard 0.18-µm complementary metal-oxide-semiconductor (CMOS) technology. The average power is 3.23 mW with 1.5 V supply voltage and the effective area is 0.0408 mm². Its division ratio ranges from 13 to 1278 at 3.5 GHz. Experimental results show that the proposed divider consumes around 30% less power compared to the conventional design.

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Low-power programmable divider with a shared counter for frequency synthesiser

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