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100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation

100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation

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Receiver timing synchronisation is a significant challenge for impulse radio ultra-wideband (IR-UWB) systems due to the low received power and narrow pulse width. In a coherent receiver, the local template pulses need to be synchronised with the received pulses with a precision of tens of picoseconds. Because of the periodic reduction in received correlated power, the traditional two-stage synchronisation method (acquisition and tracking) is not suitable for a single-path IR-UWB receiver. A tracking only, dual-loop delay-locked loop (DLL) with a 100 ps minimum phase shift is proposed to overcome this issue. This dual-loop DLL, employing a higher frequency fine loop, exhibits a better jitter transfer characteristic compared with a conventional dual-loop DLL. Measurement results of a 130 nm CMOS prototype indicate a locking frequency range of 30–120 MHz, and a best output jitter of 5.9 ps-rms (input reference jitter is 2.9 ps-rms). The total power consumption is 1.8 mW with a 1.2 V supply voltage.

Inspec keywords: synchronisation; radio receivers; delay lock loops; ultra wideband communication; jitter; CMOS analogue integrated circuits

Other keywords: frequency 30 MHz to 120 MHz; power 1.8 mW; dual-loop delay locked loop; single-path IR-UWB receiver; impulse radio ultrawideband coherent receiver synchronisation; narrow pulse width; receiver timing synchronisation; power consumption; voltage 1.2 V; CMOS prototype; received correlated power; dual loop DLL; two stage synchronisation method; jitter transfer characteristic

Subjects: Radio links and equipment; CMOS integrated circuits; Other analogue circuits

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