Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Iterative timing analysis based on nonlinear and interdependent flipflop modelling

Iterative timing analysis based on nonlinear and interdependent flipflop modelling

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered.

Inspec keywords: integrated circuit interconnections; iterative methods; flip-flops

Other keywords: nonlinear flipflop modelling; minimal clock period; digital circuit; clock-to-q delay; nonlinear functional relationship; fully interconnected analysis; interdependent system; interdependent flipflop modelling; flipflop data-clock alignment; iterative timing analysis

Subjects: Logic circuits; Interpolation and function approximation (numerical analysis); Interpolation and function approximation (numerical analysis); Metallisation and interconnection technology; Logic and switching circuits

References

    1. 1)
      • Srivastava, S., Roychowdhury, J.: `Interdependent latch setup/hold time characterization via Euler–Newton curve tracing on state-transition equations', Proc. Design Automation Conf., 2007, p. 136–141.
    2. 2)
      • Jaffari, J., Anis, M.: `On efficient Monte Carlo-based statistical static timing analysis of digital circuits', Proc. Int. Conf. on Computer-Aided Design, 2008, p. 196–203.
    3. 3)
    4. 4)
      • Chen, N., Li, B., Schlichtmann, U.: `Iterative timing analysis considering interdependency of setup and hold times', Proc. Int. Conf. on Integrated Circuit and System Design: Power and Timing Modeling, Optimization, and Simulation, 2011, p. 73–82, (LNCS, 6951).
    5. 5)
    6. 6)
    7. 7)
      • Lang, A., Bergler, S.: `Method and apparatus for circuit verification of meeting setup and hold time requirements (Verfahren und Vorrichtung zum Ueberpruefen einer Schaltung auf Einhaltung von Setup- und Holdzeiten)', German Patent DE102004044668A1, 2004.
    8. 8)
      • Singh, J., Sapatnekar, S.: `Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis', Proc. Design Automation Conf., 2006, p. 155–160.
    9. 9)
    10. 10)
      • Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: `Pessimism reduction in static timing analysis using interdependent setup and hold times', Proc. Int. Symp. on Quality Electronic Design, March 2006, p. 159–164.
    11. 11)
      • Sakallah, K.A., Mudge, T.N., Olukotun, O.A.: `Analysis and design of latch-controlled synchronous digital circuits', Proc. Design Automation Conf., 1990, p. 111–117.
    12. 12)
    13. 13)
      • Chen, N., Li, B., Schlichtmann, U.: `Timing modeling of flipflops considering aging effects', Proc. Int. Conf. on Integrated Circuit and System Design: Power and Timing Modeling, Optimization, and Simulation, 2011, p. 63–72, (LNCS, 6951).
    14. 14)
      • Hatami, S., Abrishami, H., Pedram, M.: `Statistical timing analysis of flip-flops considering codependent setup and hold times', Proc. ACM Great Lakes Symp. VLSI, 2008, p. 101–106.
    15. 15)
      • Zhang, L., Chen, W., Hu, Y., Gubner, J.A., Chen, C.C.-P.: `Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model', Proc. Design Automation Conf., 2005, p. 83–88.
    16. 16)
      • ‘The open source liberty library modeling format specification’, http://www.opensourceliberty.org/, accessed May 2012.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2011.0347
Loading

Related content

content/journals/10.1049/iet-cds.2011.0347
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address