Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
- Author(s): I. Arnaldo ; J.L. Risco-Martín ; J.L. Ayala ; J.I. Hidalgo
- DOI: 10.1049/iet-cds.2011.0350
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- Author(s): I. Arnaldo 1 ; J.L. Risco-Martín 1 ; J.L. Ayala 1 ; J.I. Hidalgo 1
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View affiliations
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Affiliations:
1: Department of Computer Architecture and Automatics (DACYA), Complutense University of Madrid, Spain
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Affiliations:
1: Department of Computer Architecture and Automatics (DACYA), Complutense University of Madrid, Spain
- Source:
Volume 6, Issue 5,
September 2012,
p.
322 – 329
DOI: 10.1049/iet-cds.2011.0350 , Print ISSN 1751-858X, Online ISSN 1751-8598
Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.
Inspec keywords: three-dimensional integrated circuits; thermal management (packaging); microprocessor chips; system-on-chip
Other keywords:
Subjects: System-on-chip; Semiconductor integrated circuits; Product packaging; Microprocessors and microcomputers; System-on-chip; Microprocessor chips
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