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FPGA-based fault emulation of synchronous sequential circuits

FPGA-based fault emulation of synchronous sequential circuits

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© The Institution of Engineering and Technology
Published

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40–500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.

Inspec keywords: logic testing; fault simulation; field programmable gate arrays

Other keywords: software-based fault simulation; FPGA-based fault emulation; flexible algorithmic test vectors; synchronous sequential circuits

Subjects: Electronic engineering computing; Logic design methods; Logic circuits

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