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Binary LNS-based naïve Bayes inference engine for spam control: noise analysis and FPGA implementation

Binary LNS-based naïve Bayes inference engine for spam control: noise analysis and FPGA implementation

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© The Institution of Engineering and Technology
Published

A hardware architecture for naïve Bayes inference engine to classify e-mail contents for spam control is proposed. The inference engine utilises the logarithmic number system (LNS) to simplify naïve Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. A noise model for the inference engine was developed and the noise bounds were analysed to determine the inference accuracy. The inference engine design is synthesised targeting the Altera Stratix field programmable gate array (FPGA) device. From the synthesis results, the binary LNS naïve Bayes inference engine was found to have the capability to classify more than 117 million features per second, given a stream of a priori and likelihood probabilities as input with small computation noise. The synthesised inference engine was functionally verified against a MATLAB implementation.

Inspec keywords: unsolicited e-mail; field programmable gate arrays; Bayes methods; inference mechanisms; pattern classification

Other keywords: FPGA device; noise model; look-up table; noniterative binary LNS recoding hardware architecture; FPGA implementation; binary LNS-based naive Bayes inference engine; Altera Stratix field programmable gate array; e-mail contents classification; noise analysis; spam control; logarithmic number system

Subjects: Logic and switching circuits; Knowledge engineering techniques; Data security; Other topics in statistics; Pattern recognition

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