The increasing bandwidth requirements of mainstream computing and consumer products, as well as the inefficiency of embedded clock interfaces in terms of latency, protocol overhead and power requirements, have caused the traditional source synchronous interfaces such as dynamic random access memory to break the Gigabit range. Above 1 Gbps dynamic effects such as drift and jitter might become critical for traditional test approaches. At the same time, the usage of dedicated source synchronous ATE HW solutions is challenged by the economic pressure and the flexibility requirements. A new test methodology based on traditional ATE architecture which can deliver both, detailed characterisation results or just a pass/fail decision for a parametric validation in production – depending on the actual test requirement – is described here.