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Bridging fault diagnostic tool based on ΔIDDQ probabilistic signatures, circuit layout parasitics and logic errors

Bridging fault diagnostic tool based on ΔIDDQ probabilistic signatures, circuit layout parasitics and logic errors

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A diagnostic tool for bridging faults combining three different data sources is presented. The first data source is a set of IDDQ measurements used to identify the most probable fault type. The second source is a list of parasitic capacitances extracted from layout and used to create a list of realistic potential bridging fault sites. The third source is logical faults detected at the primary outputs (including scan flip flops), used to limit the number of suspected gates. The combination of these data significantly reduces the number of potential fault sites to consider in the diagnosis process. Simulation results confirm that the number of potential bridging fault sites is reduced from O(N2) to less than O(N), where N is the number of nodes in the circuit. The tool therefore converges quickly towards the solution while using less resources. A new technique is also introduced to estimate the additional delay caused by the diagnosed bridging fault based on the diagnostic results. Performing this estimation allows us to confirm the previous diagnosis results.

Inspec keywords: fault location; logic gates; flip-flops; circuit layout; probabilistic logic; circuit analysis computing

Other keywords: flip flops; bridging fault diagnostic tool; circuit layout parasitics; probabilistic signatures; logic errors; parasitic capacitances

Subjects: Logic elements; Logic circuits; Electronic engineering computing; Computer-aided circuit analysis and design; Logic and switching circuits

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