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Robust paradigm for diagnosing hold-time faults in scan chains

Robust paradigm for diagnosing hold-time faults in scan chains

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  • Author(s): C.-W. Tzeng 1 ; J.-J. Hsu 2 ; S.-Y. Huang 1
    • View affiliations
    • Affiliations: 1: Department of Electrical Engineering, National Tsing-Hua University, Taiwan, Republic of China
      2: Yield Enhancement Service Section I (YES1), Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan, Republic of China
  • Source: Volume 1, Issue 6, November 2007, p. 706 – 715
    DOI:  10.1049/iet-cdt:20060205 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Published

Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failures is presented. As compared to previous methods, the main advantage of this is the ability to tolerate non-ideal conditions, for example, under the presence of certain core logic faults or for those faults that manifest themselves intermittently. The diagnosis problem is first formulated as a ‘delay insertion process’. Upon this formulation, two algorithms – a ‘greedy’ algorithm and a so-called ‘best-alignment-based’ algorithm – is proposed. Experimental results on a number of practical designs and ISCAS'89 benchmark circuits are presented to demonstrate its effectiveness.

Inspec keywords: integrated circuit layout; fault diagnosis; design for testability; integrated circuit reliability; integrated circuit testing; greedy algorithms

Other keywords: scan chains; hold-time faults diagnosis; delay insertion process; core logic faults; greedy algorithm; best-alignment-based algorithm

Subjects: Project and design engineering; Reliability; Semiconductor integrated circuit design, layout, modelling and testing

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