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Debug enhancements in assertion-checker generation

Debug enhancements in assertion-checker generation

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Published

Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead.

Inspec keywords: integrated circuit testing; integrated circuit design; logic design

Other keywords: assertion-checker generation; circuit debugging; debug enhancements; assertion circuits; design debugging; assertion debugging; verification stages; checker enhancements; silicon debug

Subjects: Digital circuit design, modelling and testing; Logic design methods

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