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Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols

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  • Author(s): T. Bengtsson 1 ; S. Kumar 1 ; R.-J. Ubar 2 ; A. Jutman 2 ; Z. Peng 3
    • View affiliations
    • Affiliations: 1: Department of Electrical Engineering and Computer Science, School of Engineering, Jönköping University, Sweden
      2: Department of Computer Engineering, Tallinn University of Technology, Estonia
      3: Department of Computer and Information Science, Linköping University, Sweden
  • Source: Volume 2, Issue 6, November 2008, p. 445 – 460
    DOI:  10.1049/iet-cdt:20070048 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Published

Variations in crosstalk is an added source of delay and glitch faults in System on Chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built with Globally Asynchronous Locally Synchronous principles. The authors propose efficient methods for at-speed testing of such faults in asynchronous links connecting, for example, two switches/routers of an network-on-chip communication infrastructure. The proposed delay test method has the property that all faulty chips are identified but some good chips may also be characterised as faulty with a small probability. The authors give an analytical analysis regarding this probability as a function of probability of delay fault and number of applied test instances. A simple and pure digital BIST hardware is also proposed, which is represented at Register Transfer level to implement the delay test method. A method is also proposed for detecting glitches on control lines in a handshaking-based communication link; thereafter it is shown how the method can be extended for detecting glitch faults on data lines. The proposed test methods for detecting delays and glitches provide a complete scheme for detection of crosstalk-induced faults in links in an on-chip communication infrastructure using asynchronous handshaking communication protocols.

Inspec keywords: built-in self test; network-on-chip; crosstalk; protocols; delays

Other keywords: network-on-chip interconnects; globally asynchronous locally synchronous principles; digital BIST hardware; system on chips; crosstalk-induced delay; asynchronous communication protocols; sub-micron technology; glitch faults; handshaking-based communication link

Subjects: Semiconductor integrated circuits; Digital circuit design, modelling and testing; Protocols; Microprocessors and microcomputers

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