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Versatile processor for GF(pm) arithmetic for use in cryptographic applications

Versatile processor for GF(pm) arithmetic for use in cryptographic applications

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© The Institution of Engineering and Technology
Published

There has been a lot of research in recent years into the implementation of cryptographic algorithms over GF(2m), GF(pm), p≥2 and GF(p), p large prime. A general architecture for a cryptographic processor capable of handling operations for elliptic curve cryptosystems and pairings over any field, and the software developed to generate it, is introduced. The processor implements a ROM instruction set to simplify control of the system and reduce hardware complexity. Efficient scheduling of the data is used to determine the optimum resource requirement for the processor. The post place and route results for a number of generated elliptic curve processors are given.

Inspec keywords: digital arithmetic; cryptography

Other keywords: elliptic curve cryptosystems; cryptographic algorithms; hardware complexity; ROM instruction set; cryptographic processor

Subjects: Cryptography theory; Digital arithmetic methods; Cryptography; Digital electronics

References

    1. 1)
      • Barreto, P., Kim, H., Lynn, B., Scott, M.: `Efficient algorithms for pairing-based cryptosystems', Advances in Cryptology - CRYPTO, Lecture Notes in Computer Science, 2002, 2442, p. 354–368.
    2. 2)
      • P. Leong , I. Leung . A microcoded elliptic curve processor using FPGA technology. IEEE Trans. VLSI Syst. , 5 , 550 - 559
    3. 3)
      • H. Wu . Bit parallel finite field multiplier and squarer using polynomial basis. IEEE Trans. Comput. , 7 , 750 - 758
    4. 4)
      • P. Barreto , S. Galbraith , C. Eigeartaigh , M. Scott . (2004) Efficient pairing computation on supersingular abelian varieties.
    5. 5)
      • N. Koblitz , A. Menezes , S. Vanstone . The state of elliptic curve cryptography. Des. Codes Cryptogr. , 173 - 193
    6. 6)
      • H. Brunner , A. Curgier , M. Hofstetter . On computing multiplicative inverses in GF(2 m). IEEE Trans. Comput. , 8 , 1010 - 1015
    7. 7)
      • Miller, V.: `Use of elliptic curves in cryptography', CRYPTO ‘85, Lecture Notes in Computer Science, 1986, 218, p. 417–426.
    8. 8)
      • V. Miller . (1986) Short programs for functions on curves.
    9. 9)
      • Bertoni, G., Breveglieri, L., Fragneto, P., Pelosi, G.: `Parallel hardware architectures for the cryptographic Tate pairing', Third Internation Conference on Information Technology: New Generations, 2006, p. 186–191.
    10. 10)
      • N. Koblitz . Elliptic curve cryptosystems. Math. Comput. , 203 - 209
    11. 11)
      • R. Brent , H.T. Kung . Systolic VLSI arrays for polynomial GCD computation'. IEEE. Trans. Comput. , 8 , 731 - 736
    12. 12)
      • I. Blake , G. Seroussi , N. Smart . Elliptic curves in cryptography.
    13. 13)
      • A. Daly , W. Marnane , E. Popovici . Fast modular inversion in the montgomery domain on reconfigurable logic. ISSC , 363 - 367
    14. 14)
      • Bertoni, G., Guajardo, J., Kumar, S., Orlando, G., Paar, C., Wollinger, T.: `Efficient GF(pm) arithmetic architectures for cryptographic applications', Topics in Cryptology – CT-RSA, Lecture Notes in Computer Science, 2003, 2612, p. 158–175.
    15. 15)
      • DS031: ‘Virtex-II platform FPGAs: complete data sheet’, available at: http://direct.xilinx.com/bvdocs/publications/ds031.pdf, 2005.
    16. 16)
      • K.K. Parhi . (1999) VLSI digital signal processing systems: design and implementation.
    17. 17)
      • Galbraith, S., Harrison, K., Soldera, D.: `Implementing the Tate pairing', Algorithm Number Theory Symposium – ANTS, Lecture Notes in Computer Science, 2002, 2369, p. 324–337.
    18. 18)
      • F. Crowe , A. Daly , W. Marnane . A scalable dual mode arithmetic unit for public key cryptosystems. ITCC , 568 - 573
    19. 19)
      • FIPS PUB 186-2: ‘Digital signature standard’. Federal Information Processing Standards Publication, US Department of Commerce/National Institute of Standards and Technology, 2000.
    20. 20)
      • Grabher, P., Page, D.: `Hardware acceleration of the Tate pairing in characteristic 3', Cryptographic Hardware and Emberdded Systems – CHES, Lecture Notes in Computer Science, 2005, 3659, p. 398–411.
    21. 21)
      • Boneh, D., Franklin, M.: `Identity-based encryption from the weil pairing', Advances in Cryptology - CRYPTO, Lecture Notes in Computer Science, 2001, 2139, p. 213–229.
    22. 22)
      • P.L. Montgomery . Modular multiplication without trial division. Math. Comput. , 519 - 521
    23. 23)
      • Kerins, T., Marnane, W., Popovici, E., Barreto, P.: `Efficient Hardware for the Tate pairing calculation in characteristic 3', Cyrptographic hardware and Embedded Systems – CHES, Lecture Notes in Computer Science, 2003, 3659, p. 412–426.
    24. 24)
      • K. Watanabe , N. Takagi , K. Takagi . A VLSI algorithm for division in GF(2m) based on the extended binary GCD algorithm,. IEICE Trans. Fundam. , 5 , 994 - 999
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