Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Methodology to derive context adaptable architectures for FPGAs

Methodology to derive context adaptable architectures for FPGAs

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The configurable nature of field-programmable gate arrays (FPGAs) has allowed designers to take advantage of various data flow characteristics in application kernels to create custom architecture implementations, by optimising instruction level paralleism (ILP) and pipelining at the register transfer level. However, not all applications are composed of pure data flow kernels. Intermingling of control and data flows in applications offers more interesting challenges in creating custom architectures. The authors present one possible way to take advantage of correlations that may be present among data flow graphs (DFGs) embedded in control flow graphs. In certain cases, where there is sufficient correlation and ILP, the proposed context adaptable architecture (CAA) design methodology results in an interesting and useful custom architecture for such embedded DFGs. Certain other application characteristics may demand the use of alternative methodologies such as partial and dynamic reconfiguration (PDR) and a mixture of PDR and common sub-graph methods (PDR-CSG). The authors present a rigorous analysis, combined with some benchmarking efforts to showcase the differences, advantages and disadvantages of the CAA methodology with other methodologies. The authors also present an analysis of how the core underlying algorithm in our methodology compares with other published algorithms and the differences in resulting designs on an FPGA for a sample set of test cases.

References

    1. 1)
      • Mesquita, D., Moraes, F., Palma, J., Moller, L., Calazans, N.: `Remote and partial reconfiguration of FPGAs: tools and trends', Int. Parallel and Distributed Processing Symp., 2003.
    2. 2)
      • Dasu, A., Panchanathan, S.: `A methodology to design a dynamically reconfigurable media processor', MASES workshop/CASES, 2003, San Jose, California.
    3. 3)
    4. 4)
      • Cicirello, V.A., Regli, W.C.: `Resolving non-uniqueness in design feature histories', Proc. 7th ACM Symp. Solid Modeling and Applications, 1999.
    5. 5)
    6. 6)
      • T. Grotker , S. Liao , G. Martin , S. Swan . (2002) System design with system C.
    7. 7)
      • http://www.xilinx.com/products/design_resources/design_tool/index.htm, accessed October 2007.
    8. 8)
      • http://direct.xilinx.com/bvdocs/publications/ds112.pdf, accessed October 2007.
    9. 9)
      • Singhal, L., Bozorgzadeh, E.: `Physically-aware exploitation of component reuse in a partially reconfigurable architecture', Int. Parallel and Distributed Processing Symp., 25–29 April 2006.
    10. 10)
      • Guo, Y., Gerard, J., Broersma, H., Heysters, P.: `Template Generation and Selection Algorithms', Proc. 3rd IEEE Int. Workshop on System-on-a-Chip for Real-Time Applications, 2003, p. 2–5.
    11. 11)
      • Raghavan, A., Sutton, P.: `JPG – a parital bitstream generation tool to support partial reconfiguration in virtex FPGAs', Int. Parallel and Distributed Processing Symp., 15–19 April 2002, p. 155–160.
    12. 12)
    13. 13)
    14. 14)
      • A. Dasu , A. Sudarsanam , S. Panchanathan . Design of embedded compute intensive processing elements and their scheduling in a reconfigurable environment. Can. J. Electr. Comput. Eng. , 2 , 103 - 113
    15. 15)
      • Gericota, M., Alves, G., Silva, M., Ferreira, J.: `Run-time management of logic resources on reconfigurable systems', Design, Automation and Test in Europe, 2003, p. 974–979.
    16. 16)
      • Cicirello, V.A., Smith, S.F.: `Modeling GA performance for control parameter optimization', GECCO, 2000.
    17. 17)
      • Ferrandi, F., Santambrogio, M., Sciuto, D.: `A design methodology for dynamic reconfiguration: the Caronte architecture', 19thIEEE Int. Parallel and Distributed Processing Symp., 4–8 April 2005.
    18. 18)
      • Bunke, H.: `A comparison of algorithms for maximum common subgraph of randomly connected graphs', Proc. Joint IAPR Int. Workshop on Structural, Syntactic, and Statistical Pattern Recognition, 2002, p. 123–132.
    19. 19)
      • O. Diessel , G. Milne . Hardware compiler realising concurrent processes in reconfigurable logic. IEE Proc. Comput. Digit. Tech. , 45 , 52 - 62
    20. 20)
      • Heng, T., Demara, R.: `A physical resource management approach to minimizing FPGA partial reconfiguration overhead', IEEE Int. Conf. Reconfigurable Computing and FPGAs, 2006, p. 1–5.
    21. 21)
      • Cicirello, V.A., Regli, W.C.: `Matching feature based comparisons of mechanical parts', Proc. 7th ACM Symp. Solid Modeling and Applications, 2002, p. 273–280.
    22. 22)
      • Foggia, P., Sansone, C., Vento, M.: `An improved algorithm for matching large graphs', Proc. 3rd IAPR-TC15 Workshop on Graph-based Representations, 2001.
    23. 23)
      • Dasu, A., Sudarsanam, A.: `High level – application analysis techniques and architectures – to explore design possibilities for reduced reconfiguration area overheads in FPGAs executing compute intensive applications', 19thIEEE Int. Parallel and Distributed Processing Symp. – reconfigurable architectures workshop, 2005, Denver, Colorado, p. 158.
    24. 24)
      • http://www.mpi-sb.mpg.de/BALL, accessed October 2007.
    25. 25)
      • Nasi, K., Karouhalis, T., Danek, M., Pohl, Z.: `FIGARO – an automatic tool flow for designs with dynamic reconfiguration', Int. Conf. Field Programmable Logic and Applications, 24–26 August 2005, p. 590–593.
    26. 26)
      • http://www.gnu.org/software/gsl, accessed October 2007.
    27. 27)
      • Cong, J., Fan, Y., Han, G., Zhang, Z.: `Application-Specific Instruction Generation for Configurable Processor Architectures', 12thInt. Symp. Field Programmable Gate Arrays, 2004, p. 183–189.
    28. 28)
      • Carvalho, E., Calazans, N., Brio, E., Moraes, F.: `PaDReH – a framework for the design and implementation of dynamically and partially reconfigurable systems', 17thSymp. Integrated Circuits and Systems Design, 7–11 September 2004, p. 10–15.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20070099
Loading

Related content

content/journals/10.1049/iet-cdt_20070099
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address