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Optimal subgraph covering for customisable VLIW processors

Optimal subgraph covering for customisable VLIW processors

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© The Institution of Engineering and Technology
Published

It is increasingly common to see the combination of single-issue general purpose processors (GPPs) with extensible VLIW processors in many embedded system designs. Compared with GPPs, extensible VLIW processors can exploit instruction-level parallelism, and they are more suitable for computation-intensive tasks. Moreover, they offer the ability of customising instruction-set extensions (ISEs) for an application domain. Many previous works reveal that automated extension generation can greatly improve both performance and design efficiency of instruction-set extensible processors. One of the key steps of automated extension generation is subgraph selection. Since this problem is at least NP-hard, most previous works rely on greedy approaches to address it, whereas an optimal subgraph mapping methodology that customises ISEs for multi-issue/VLIW extensible processors is presented here. Several effective pruning techniques are proposed to ensure that the proposed methodology is tractable, and the optimal method performs 41.02% better than greedy method on average. Besides the optimal subgraph covering methodology, several techniques are also proposed to reduce the area burden that ISEs impose on the processor.

Inspec keywords: graph theory; instruction sets; application specific integrated circuits; microprocessor chips

Other keywords: optimal subgraph covering; pruning techniques; customisable VLIW processors; instruction-level parallelism; single-issue general purpose processors; instruction-set extensions; NP-hard

Subjects: Microprocessors and microcomputers; Microprocessor chips; Combinatorial mathematics; Combinatorial mathematics

References

    1. 1)
      • Atasu, K., Pozzi, L., Ienne, P.: `Automatic application-specific instruction-set extensions under microarchitectural constraints', Proc. Design Automation Conf, June 2003, Anaheim, CA, USA, p. 256–261.
    2. 2)
      • Gschwind, M.: `Instruction set selection for ASIP design', Proc. Workshop on Hardware/Software Codesign, May 1999, p. 7–11.
    3. 3)
      • Arnold, M., Corporaal, H.: `Designing domain specific processors', Proc. Int. Symp. Hardware/Software Codesign, April 2001, Copenhagen, Denmark, p. 61–66.
    4. 4)
      • Available at: http://www.trimaran.com, accessed February 2008.
    5. 5)
      • Available at: http://www.st.com/, accessed October 2007.
    6. 6)
      • Clark, N., Hormati, A., Mahlke, S., Yehia, S.: `Scalable subgraph mapping for acyclic computation accelerators', Proc. Int. Conf. Compilers, Architecture and Synthesis for Embedded Systems, October 2006, Seoul, Korea, p. 147–157.
    7. 7)
      • D. Seal . (2000) ARM architecture reference manual.
    8. 8)
      • Peymandoust, A., Pozzi, L., Ienne, P., De Micheli, G.: `Automatic instruction set extension and utilization for embedded processors', Proc. IEEE Int. Conf. Application-Specific Systems, Architectures and Processors, June 2003, Hague, The Netherlands, p. 108–118.
    9. 9)
      • Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: `MiBench: A free, commercially representative embedded benchmark suite', IEEE 4th Workshop on Workload Characterization, December 2001, Austin, Texas, USA, p. 3–14.
    10. 10)
      • Lee, C., Potkonjak, M., Smith-Mangione, W.H.: `MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems', Proc. Int. Symp. Microarchitecture, Research Triangle Park, December 1997, North Carolina, USA, p. 330–335.
    11. 11)
      • Pozzi, L., Ienne, P.: `Exploiting pipelining to relax register-file port constraints of instructionset extensions', Proc. 2005 Int. Conf. Compilers, Architectures and Synthesis for Embedded Systems, September 2005, San Francisco, California, USA, p. 2–10.
    12. 12)
      • Available at: http://www.semicon.toshiba.co.jp/eng/product/micro/mep/index.html, accessed October 2007.
    13. 13)
      • Clark, N., Zhong, H., Mahlke, S.: `Processor acceleration through automated instruction set customization', Proc. 36th Annual Int. Symp. Microarchitecture, December 2003, San Diego, CA, USA, p. 129–140.
    14. 14)
      • Yu, P., Mitra, T.: `Scalable custom instructions identification for instruction-set extensible processors', Proc. Int. Conf. Compilers, Architecture and Synthesis for Embedded Systems, September 2004, Washington DC, USA, p. 69–78.
    15. 15)
      • Sun, F., Ravi, S., Raghunathan, A., Jha, N.K.: `A scalable application-specific processor synthesis methodology', Proc. Int. Conf. Computer Aided Design, November 2003, San Jose, CA, USA, p. 283.
    16. 16)
      • N.T. Clark , H. Zhong , S.A. Mahlke . Automated custom instruction generation for domain-specific processor acceleration. IEEE Trans. Comput. , 10 , 1258 - 1270
    17. 17)
      • Yu, P., Mitra, T.: `Characterizing embedded applications for instruction-set extensible processors', Design Automation Conf., June 2004, San Diego, CA, p. 723–728.
    18. 18)
      • Pothineni, N., Kumar, A., Paul, K.: `Application specific datapath extension with distributed I/O functional units', Proc. 20th Int. Conf. VLSI Design, January 2007, Bangalore, India, p. 551–558.
    19. 19)
      • Alomary, A., Nakata, T., Honma, Y., Sato, J., Hikichi, N., Imai, M.: `PEAS-I: a hardware/software co-design system for ASIPs', Proc. European Design Automation Conf., September 1993, Hamburg, Germany, p. 2–7.
    20. 20)
      • Brisk, P., Kaplan, A., Kastner, R., Sarrafzadeh, M.: `Instruction generation and regularity extraction for reconfigurable processors', Proc. CASES, October 2002, Grenoble, France, p. 262–269.
    21. 21)
      • Available at: http://www.xtensa.com/, accessed October 2007.
    22. 22)
      • Cong, J., Fan, Y., Han, G., Zhang, Z.: `Application-specific instruction generation for configurable processor architectures', The 12th Int. Symp. Field Programmable Gate Arrays, Feburary 2004, Monterey, California, USA, p. 183–189.
    23. 23)
      • Bonzini, P., Pozzi, L.: `Polynomial-time subgraph enumeration for automated instruction set extension', Proc. Conf. Design, Automation and Test in Europe, April 2007, Nice, France, p. 1331–1336.
    24. 24)
      • X. Chen , D. Maskell , Y. Sun . Fast identification of custom instructions for extensible processors. IEEE Trans. Comput.-Aided Des. of Integ. Circuits Syst. , 2 , 359 - 368
    25. 25)
      • Lee, J.-E., Choi, K., Dutt, N.: `Efficient instruction encoding for automatic instruction set design of configurable ASIPs', Proc. Int. Conf. Computer-Aided Design, November 2002, San Jose, California, p. 649–654.
    26. 26)
      • X. Chen , D.L. Maskell . Supporting multiple-input, multiple-output custom functions in configurable processors. J. Syst. Archit. , 263 - 271
    27. 27)
      • Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., Flautner, K.: `An architecture framework for transparent instruction set customization in embedded processors', Proc. 32nd Annual Int. Symp. Computer Architecture, June 2005, Madison, Wisconsin, USA, p. 272–283.
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