Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Design networks-on-chip with latency/bandwidth guarantees

Design networks-on-chip with latency/bandwidth guarantees

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

A method is proposed to guarantee bandwidth (BW) or latency of network-on-chip. This method contains three kernels: traffic classification; flit-based switching; path pre-assignment and link-BW setting. Compared with the traditional circuit-switch method, the proposed method can guarantee the latency between one flit's generation in the source node and its reception in the destination node. This method also supports a wide range of traffic types such as latency critical, low BW traffic and streaming data which only have BW requirement. Moreover, router and network interface which support the proposed method are implemented and a maximum latency formula is developed. Simulation and synthesis results show that this method can guarantee the BW and latency well and is relatively low cost.

Inspec keywords: network interfaces; circuit switching; network-on-chip; logic design

Other keywords: traffic classification; router; flit-based switching; network interface; link bandwidth setting; network-on-chip design

Subjects: Logic design methods; Microprocessor chips; Microprocessors and microcomputers; Digital circuit design, modelling and testing

References

    1. 1)
      • MillBerg, M., Nilsson, E., Thid, R., Jantsch, A.: `Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip', Proc. IEEE Conf. Design, Automation and Test, February 2004, Paris, France, p. 890–895.
    2. 2)
    3. 3)
    4. 4)
      • Scheffer, L.: `Methodologies and tools for pipelined on-chip interconnect', Proc. IEEE Conf. Computer Design: VLSI in Computers and Processors, September 2002, San Jose, CA, USA, p. 152–157.
    5. 5)
      • Rijpkema, E., Goossens, K., Radulescu, A.: `Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip', Proc. IEEE Conf. Design, Automation and Test, March 2003, Munich, Germany, p. 350–355.
    6. 6)
      • Kanishka, L.: `On-chip communication: system-level architectures and design methodologies', 2003, PhD, University of California.
    7. 7)
      • Harmanci, M.D., Escudero, N.P., Leblebici, Y., Ienne, P.: `Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities', Proc. IEEE Conf. System-on-Chip, November 2004, Tampere, Finland, p. 37–40.
    8. 8)
    9. 9)
      • R. Gupta . On-chip networks. IEEE Des. Test Comput. , 5 , 393 - 393
    10. 10)
      • Felicijan, T., Furber, S.B.: `An asynchronous on-chip network router with quality-of-service (QoS) support', Proc. IEEE Conf. System-on-Chip, November 2004, Tampere, Finland, p. 274–277.
    11. 11)
      • A. Ivanov , G.D. Micheli . The network-on-chip paradigm in practice and research. IEEE Des. Test Comput. , 5 , 399 - 403
    12. 12)
      • P.P. Pande , C. Grecu , M. Jones . Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. , 8 , 1025 - 1040
    13. 13)
      • L. Benini , G. De Micheli . Networks on chips: a new SoC paradigm. IEEE Comput. , 1 , 70 - 78
    14. 14)
      • L. Anthony , M. Dragomir , V. Diederik , R. Frederic , C. Francky . Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip. IEEE Trans. Comput. , 9 , 1182 - 1195
    15. 15)
    16. 16)
      • Bjerregaard, T., Sparso, J.: `Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip', Proc. IEEE Conf. Asynchronous Circuits and Systems, March 2005, NY, USA, p. 34–43.
    17. 17)
    18. 18)
    19. 19)
      • Terry, T.: `On-chip multiprocessor communication network design and analysis', 2003, PhD, Stanford University.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20080036
Loading

Related content

content/journals/10.1049/iet-cdt_20080036
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address