Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
- Author(s): J.E. Rice and K.B. Kent
- DOI: 10.1049/iet-cdt.2008.0042
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- Author(s): J.E. Rice 1 and K.B. Kent 2
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View affiliations
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Affiliations:
1: Department of Math and Computer Science, University of Lethbridge, Lethbridge, Canada
2: Faculty of Computer Science, University of New Brunswick, Fredericton, Canada
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Affiliations:
1: Department of Math and Computer Science, University of Lethbridge, Lethbridge, Canada
- Source:
Volume 3, Issue 3,
May 2009,
p.
247 – 258
DOI: 10.1049/iet-cdt.2008.0042 , Print ISSN 1751-8601, Online ISSN 1751-861X
Reconfigurable hardware has recently shown itself to be an appropriate solution to speeding up problems that are highly dependent on a particular complex or repetitive sub-algorithm. In most cases, these types of solutions lend themselves well to parallel solutions. The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised is investigated. In addition, a classification system is introduced, which categorises FPGA-based solutions into ‘instance-specific’ and ‘parameter-specific’.
Inspec keywords: reconfigurable architectures; field programmable gate arrays; parallel processing
Other keywords:
Subjects: Logic circuits; Logic and switching circuits
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