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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

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© The Institution of Engineering and Technology
Published

Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

Inspec keywords: network-on-chip; design for testability; network topology; asynchronous circuits; automatic test pattern generation; logic design; logic testing; network routing

Other keywords: asynchronous network-on-chip architecture; network topology; post-fabrication testing; test pattern generation; design-for-test approach; network router

Subjects: Automatic test systems; Microprocessor chips; Microprocessors and microcomputers; Digital circuit design, modelling and testing; Logic design methods

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