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Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips

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The study proposes a new concept of test and diagnosis in regular mesh-like network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As it will be shown, such configurations can be applied for achieving near-100% structural fault coverage for the network switches. Additionally, a concept of functional switch faults, called link faults, is introduced. The approach is scalable (complexity grows linearly with respect to the number of switches) and it is capable of unambigously pinpointing the faulty links inside the switching network. Current paper also presents a set of design-for-testability (DfT) techniques for the application of test patterns from the external boundary of a NoC. The authors have implemented a parametrisable switching network and developed a set of DfT structures to support testing of network switches using external test configurations. The proposed structures include resource loopback for testing the crossbar multiplexer of the resource connection, a modification to the control part to force YX routing and a compact logic built-in self test (BIST) for the control unit. Experiments show that the proposed structures allow near-100% test coverage at the expense of less than 4% of extra switch area.

Inspec keywords: design for testability; network-on-chip; built-in self test

Other keywords: design-for-testability-based external test; resource loopback; YX routing; test patterns application; crossbar multiplexer; regular mesh-like network-on-a-chip designs; built-in self test; functional switch faults; link faults; network switches; functional fault models; resource connection

Subjects: Microprocessors and microcomputers; Digital circuit design, modelling and testing; Microprocessor chips

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