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Fault tolerance and reliability in field-programmable gate arrays

Fault tolerance and reliability in field-programmable gate arrays

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© The Institution of Engineering and Technology
Published

Reduced device-level reliability and increased within-die process variability will become serious issues for future field-programmable gate arrays (FPGAs), and will result in faults developing dynamically during the lifetime of the integrated circuit. Fortunately, FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome such degradation-induced faults. This study provides a comprehensive survey of fault detection methods and fault-tolerance schemes specifically for FPGAs and in the context of device degradation, with the goal of laying a strong foundation for future research in this field. All methods and schemes are quantitatively compared and some particularly promising approaches are highlighted.

Inspec keywords: fault location; logic testing; fault tolerance; reliability; field programmable gate arrays

Other keywords: field programmable gate arrays; degradation induced faults; fault tolerance; device level reliability

Subjects: Logic design methods; Reliability; Digital circuit design, modelling and testing; Logic circuits; Logic and switching circuits

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