Methodology to derive resource aware context adaptable architectures for FPGAs

H. Samala; A. Dasu

Methodology to derive resource aware context adaptable architectures for FPGAs

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Methodology to derive resource aware context adaptable architectures for FPGAs

Author(s): H. Samala and A. Dasu
DOI: 10.1049/iet-cdt.2009.0047

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Author(s): H. Samala ¹ and A. Dasu ¹
- Affiliations: 1: Department of Electrical and Computer Engineering, Utah State University, Logan, USA
Source: Volume 4, Issue 1, January 2010, p. 73 – 88
DOI: 10.1049/iet-cdt.2009.0047 , Print ISSN 1751-8601, Online ISSN 1751-861X

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The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a field programmable gate array (FPGA) with heterogeneous mixture of device primitives. In this study, the authors present scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. The authors present the results of a rigorous analysis of the methodology on multiple test cases. Post place and route results are compared against published techniques and show an area savings and execution time savings of 46% each.

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