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Low-power dual-edge triggered state-retention scan flip-flop

Low-power dual-edge triggered state-retention scan flip-flop

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© The Institution of Engineering and Technology
Published

This study presents a dual-edge triggered static scanable flip-flop suitable for low-power applications. The proposed circuit deploys reduced swing-clock and swing-data to manage dynamic power. Furthermore, it employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The static structure of the circuit makes it feasible to be used in variable frequency power control designs. HSPICE post-layout simulation conducted for 90 nm complementary metal-oxide semiconductor technology indicates that in addition to state retention and test capability, the proposed design, in terms of power-delay product, device count and leakage power is comparable to other high-performance flip-flops.

Inspec keywords: flip-flops; power aware computing; CMOS integrated circuits

Other keywords: static power; low-power dual edge triggered state-retention scan flip-flop; dynamic power; circuit deployment; power delay product; frequency power control designs; post layout simulation; power gating

Subjects: Logic and switching circuits; Logic circuits; Other circuits for digital computers; CMOS integrated circuits

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