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State encoding algorithm for peak current minimisation

State encoding algorithm for peak current minimisation

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As the silicon process technology advances, chip reliability becomes more and more important. One of the critical factors that affect the chip reliability is the peak current in the circuit. In particular, high current peaks at the time of state transition in synchronous finite state machine (FSM) circuits often make the circuits very unstable in execution. This work addresses the state encoding problem with the objective of minimising peak current in FSMs. Unlike the previous power-aware state encoding algorithms, where the primary objective is to reduce the amount of switching activities of state register and the problem of reducing peak current has not been addressed at all or considered as a secondary objective, which obviously severely limits the search space of state encoding for minimising peak current, our algorithm, called SAT-pc, places the importance on the reliability, that is, peak current. Specifically, the authors solve two important state encoding problems in two phases: (Phase 1) the authors present a solution to the problem of state encoding for directly minimising peak current, by formulating it into the SAT problem with pseudo-Boolean expressions, which leads to a full exploration of the search space; (Phase 2) the authors then propose an efficient SAT-based heuristic to solve the state re-encoding problem for minimising switching power without deteriorating the minimum peak current obtained in Phase 1. Through an experimentation using MCNC benchmarks, it is shown that SAT-pc is able to reduce the peak current by 51 and 35%, compared to POW3 [4] that minimises the switching power only and POW3[14] + [24] that minimises the switching power and then peak current, respectively.

Inspec keywords: Boolean algebra; minimisation; VLSI; finite state machines

Other keywords: chip reliability; state encoding algorithm; peak current minimisation; synchronous finite state machine circuits; pseudo-Boolean expressions

Subjects: Digital electronics; Optimisation techniques; Algebra

References

    1. 1)
    2. 2)
      • Bobba, S., Hajj, I.: `Estimation of maximum current envelope for power bus analysis and design', Proc. Int. Symp. on Physical Design, April 1998, p. 141–146.
    3. 3)
      • Yuan, L., Qu, G.: `FSM re-engineering for low power state encoding', Proc. Int. Workshop on Logic Synthesis, June 2004, p. 257–264.
    4. 4)
      • Liu, B.: `Maximum instantaneous power estimation by subgraph coloring', CS2005-0834, UCSD Technical, 2005.
    5. 5)
      • Huang, S.H., Chang, C.M., Nieh, Y.T.: `State re-encoding for peak current minimization', Proc. Int. Conf. on Computer-Aided Design, November 2006, p. 33–38.
    6. 6)
      • Jacobs, E., Berkelaar, M.: `A linear programming approach for the estimation of an upper bound on the maximum power of CMOS circuits', Proc. Int. Workshop on Logic Synthesis, July 1998, p. 201–206.
    7. 7)
      • ftp://mcnc.mcnc.org, Logic Synthesis 1991.
    8. 8)
      • B.W. Kernighan , S. Lin . An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. , 1 , 291 - 307
    9. 9)
      • Tsui, C.Y., Pedram, M., Despain, A.M.: `Low power state assignment targeting two and multilevel logic implementations', Proc. Int. Conf. on Computer-Aided Design, November 1994, p. 82–87.
    10. 10)
      • Hachtel, G., Hermida, M., Pardo, A., Poncino, M., Somenzi, F.: `Re-encoding sequential circuits to reduce power dissipation', Proc. Int. Conf. on Computer-Aided Design, November 1994, p. 70–73.
    11. 11)
      • Noth, W., Kolla, R.: `Spanning tree based state encoding for low power', Proc. Design Automation and Test in Europe, March 1999, p. 168–174.
    12. 12)
    13. 13)
      • Aloul, F., Ramani, A., Markov, I., Sakallah, K.: `PB-Solver: a backtrack-search pseudo-Boolean solver and optimizer', Proc. Symp. on Theory and Applications of Satisfiability Testing, October 2002, p. 346–353.
    14. 14)
      • Chandy, A., Chen, T.: `Performance driven decoupling capacitor allocation considering data and clock interactions', Proc. Design Automation and Test in Europe, March 2005, p. 984–985.
    15. 15)
      • Gao, F., Hayes, J.P.: `ILP-based optimization of sequential circuits for low power', Proc. Int. Symp. on Low Power Electronics and Design, August 2003, p. 140–145.
    16. 16)
      • Kumthekar, B., Macii, E., Poncino, M., Somenzi, F.: `Simulation-based re-synthesis of sequential circuits for peak sustainable power reduction', Proc. Int. Workshop on Logic Synthesis, July 1998, p. 392–397.
    17. 17)
      • Chen, P.-Y., Liu, C.-Y., Hwang, T.: `Transition-aware decoupling capacitor allocation in power noise reduction', Proc. Int. Conf. on Computer-Aided Design, November 2008, p. 426–429.
    18. 18)
      • Hsiao, M.S.: `Peak power estimation using genetic spot optimization for large VLSI circuits', Proc. Design Automation and Test in Europe, March 1999, p. 175–179.
    19. 19)
      • Yeh, C.-Y., Marek-Sadowska, M.: `Timing-aware power noise reduction in layout', Proc. Int. Conf. on Computer-Aided Design, November 2005, p. 627–634.
    20. 20)
      • Benini, L., Vermeulen, F., Micheli, G.D.: `Finite-state machine partitioning for low-power', Proc. Int. Symp. on Circuits and Systems, May 1998, p. 5–8.
    21. 21)
      • Aloul, F., Hassoun, S., Sakallah, K., Blaauw, D.: `Robust SAT-based search algorithm for leakage power reduction', Proc. Int. Workshop on Power and Timing Modeling, Optimization and Simulation, September 2002, p. 167–177.
    22. 22)
    23. 23)
    24. 24)
      • Olson, E., Kang, S.M.: `State assignment for low power FSM synthesis using genetic local search', Proc. Custom Integrated Circuits and Conf., September 1994, p. 140–143.
    25. 25)
    26. 26)
    27. 27)
      • Cao, C., Oelmann, B.: `Mixed synchronous/asynchronous state memory for low power FSM design', Proc. Digital System Design, EUROMICRO Systems, September 2004, p. 363–370.
    28. 28)
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