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Static test compaction for diagnostic test sets of full-scan circuits

Static test compaction for diagnostic test sets of full-scan circuits

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The authors describe a static test compaction procedure for diagnostic test sets of full-scan circuits. Similar to reverse order and random order fault simulation procedures applied to fault detection test sets, the procedure simulates the test set in different orders in order to identify unnecessary tests. Two features distinguish the procedure from earlier ones. (i) It uses a diagnostic fault simulation process based on equivalence classes to identify tests that are not necessary for distinguishing fault pairs. (ii) It includes an iterative reordering process whose goal is to increase the number of tests that will be identified as unnecessary. Experimental results are presented to demonstrate the ability of the procedure to compact diagnostic test sets and the effectiveness of the iterative reordering process.

Inspec keywords: circuit testing; iterative methods; fault simulation

Other keywords: full-scan circuits; iterative reordering process; static test compaction; diagnostic fault simulation process; diagnostic test sets; fault detection test sets

Subjects: Interpolation and function approximation (numerical analysis); Digital circuit design, modelling and testing

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