Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

References

    1. 1)
      • Chiou, L.-Y., Lou, S.-C.: `An energy-efficient dual-edge triggered level-converting flip-flop', IEEE Int. Symp. on Circuits and Systems, May 2007, p. 1157–1160.
    2. 2)
      • Nedovic, N., Walker, W.W., Oklobdzija, V.G., Aleksic, M.: `A low power symmetrically pulsed dual edge–triggered flip–flop', Proc. 28th European Solid-State Circuits Conf., September 2002, p. 399–402.
    3. 3)
      • K.M.G.V. Gettings , D.S. Boning . Study of CMOS process variation by multiplexing analog characteristics. IEEE Trans. Semiconductor Manuf. , 4 , 513 - 525
    4. 4)
      • Jie, Y.: `Manufacturability aware design', 2007, PhD, University of Michigan.
    5. 5)
      • S. Kim , C.H. Ziesler , M.C. Papaefthymiou . Charge-recovery computing on silicon. IEEE Trans. Comput. , 6 , 651 - 659
    6. 6)
      • N. Nedovic , V.G. Oklobdzija . Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 5 , 577 - 590
    7. 7)
      • V.S. Sathe , J.C. Kao , M.C. Papaefthymiou . Resonant-clock latch-based design. IEEE J. Solid-State Circuits , 4 , 864 - 873
    8. 8)
      • Nedovic, N., Aleksic, M., Oklobdzija, V.G.: `Timing characterization of dual-edge triggered flip-flops', Proc. Int. Conf. on Computer Design, September 2001, p. 538–541.
    9. 9)
      • Sarkar, P., Koh, C.K.: `Repeater block planning under simultaneous delay and transition time constraints', Design, Automation and Test in Europe Conf. and Exhibition, 2001, p. 540–544.
    10. 10)
      • Cooke, M., Mahmoodi-Meimand, H., Roy, K.: `Energy recovery clocking scheme and flip-flops for ultra low energy applications', Proc. Int. Symp. on Low Power Electronics and Design, August 2003, p. 54–59.
    11. 11)
      • Tawfik, S.A., Kursun, V.: `Dual-VDD clock distribution for low power and minimum temperature fluctuations induced skew', Proc. Eighth Int. Symp. on Quality Electronic Design, March 2007, p. 73–78.
    12. 12)
    13. 13)
      • Hu, Y., Li, Z., Zhou, R.: `A new type of high-performance low-power low clock-swing TSPC flip-flop', Seventh Int. Conf. on ASIC, October 2007, p. 130–133.
    14. 14)
      • S.C. Chan , P.J. Restle , T.J. Bucelot . A resonant global clock distribution for the cell broadband engine processor. IEEE J. Solid State Circuits , 1 , 64 - 72
    15. 15)
      • Masuda, H., Okawa, S., Aoki, M.: `Approach for physical design in sub-100 nm era', IEEE Int. Symp. on Circuits and Systems, 2005, 6, p. 5934–5937.
    16. 16)
      • Kim, C., Kang, S.M.: `A low-swing clock doubled-edge triggered flip-flop', Symp. on VLSI Circuits, June 2001, p. 183–186.
    17. 17)
      • Liu, Y.-T., Chiou, L.-Y., Chang, S.-J.: `Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop', IEEE Int. Symp. on Circuits and Systems, 2006, p. 4329–4332.
    18. 18)
      • Cordero, V.H., Khatri, S.P.: `Clock distribution scheme using coplanar transmission lines', Design, Automation, and Testing in Europe, March 2008, p. 985–990.
    19. 19)
      • Liu, Y.-T., Chiou, L.Y., Chang, S.-J.: `Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop', ISCAS, 2006, p. 4329–4332.
    20. 20)
    21. 21)
      • Carbognani, F., Buergin, F., Felber, N., Kaeslin, H., Fichtner, W.: `Two-phase resonant clocking for ultra-low-power hearing aid applications', Proc. Design, Automation, and Test in Europe, 2006, 1, p. 1–6.
    22. 22)
      • Esmaeili, S.E., Al-Khalili, A.J., Cowan, G.E.R.: `Dual-edge triggered energy recovery DCCER flip-flop for low energy applications', European Conf. on Circuit Theory and Design, ECCTD, August 2009, p. 57–60.
    23. 23)
      • Tirumalashetty, V., Mahmoodi, H.: `Clock gating and negative edge triggering for energy recovery clock', IEEE Int. Symp. on Circuits and Systems, May 2007, p. 1141–1144.
    24. 24)
      • Kwon, Y., Park, B., Park, I., Kyung, C.: `A new single-clock flip-flop for half-swing clocking', Proc. Asia and South Pacific Design Automation Conf., ASP-DAC'99, 1999, 1, p. 117–120.
    25. 25)
      • Hofstee, P., Aoki, N., Boerstler, D.: `1 GHz single-issue 64 b PowerPC processor', IEEE Solid-State Circuits Conf., February 2000, p. 92–93.
    26. 26)
      • N. Nedovic , V.G. Oklobdzija . Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 5 , 557 - 590
    27. 27)
      • Taskin, B., Wood, J., Kourtev, I.S.: `Timing-driven physical design for VLSI circuits using resonant rotary clocking', IEEE Int. Midwest Symp. on Circuits and Systems, 1 August 2006, p. 261–265.
    28. 28)
      • Ghadiri, M.H.: `Dual-edge triggered static pulsed flip-flops', 18thInt. Conf. on VLSI Design, 2005, p. 846–849.
    29. 29)
      • S.E. Esmaeili , A.M. Farhangi , A.J. Al-Khalili , G.E.R. Cowan . Skew compensation in energy recovery clock distribution networks. IET Comput. Digital Tech. , 1 , 56 - 72
    30. 30)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0005
Loading

Related content

content/journals/10.1049/iet-cdt.2010.0005
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address