Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Verification by parts: reusing component invariant checking results

Verification by parts: reusing component invariant checking results

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

This study explores the utility of reusing proven component invariants in the backward reachability-based sequential equivalence checking paradigm of formal verification. The authors present a formal method for simplifying the process of proving global invariants on an integrated design using the reachability information of the component state spaces, obtained from known invariants for the components of the design. Experimental results on benchmark circuits reveal that deriving the approximate reachability don't cares from the proofs of component invariants helps in reducing both the depth and breadth of the search.

Inspec keywords: reachability analysis; formal verification

Other keywords: backward reachability; formal verification; reachability information; benchmark circuits; component invariant; sequential equivalence

Subjects: Diagnostic, testing, debugging and evaluating systems; Formal methods

References

    1. 1)
      • Govindaraju, S.G., Dill, D.L.: `Verification by approximate forward and backward reachability', ICCAD ’98: Proc. 1998 IEEE/ACM Int. Conf. on Computer-Aided Design, 1998, New York, NY, USA, p. 366–370.
    2. 2)
      • Cudd: ‘Cu decision diagram package’, http://vlsi.colorado.edu/ fabio/CUDD/.
    3. 3)
      • Moon, I.-H., Jang, J.-Y., Hachtel, G.D., Somenzi, F., Yuan, J., Pixley, C.: `Approximate reachability don't cares for CTL model checking', ICCAD ’98: Proc. 1998 IEEE/ACM Int. Conf. on Computer-aided Design, 1998, New York, NY, USA, p. 351–358.
    4. 4)
      • Stergiou, S., Jain, J.: `Disjunctive transition relation decomposition for efficient reachability analysis', IEEE Int. High-Level Design, Validation, and Test Workshop, 2006, p. 29–36.
    5. 5)
      • Coudert, O., Berthet, C., Madre, J.C.: `Verification of synchronous sequential machines based on symbolic execution', Proc. Int. Workshop on Automatic Verification Methods for Finite State Systems, 1990, New York, NY, USA, p. 365–373.
    6. 6)
      • Ranjan, R.K., Aziz, A., Brayton, R.K., Plessier, B., Pixley, C.: `Efficient BDD algorithms for FSM synthesis and verification', IEEE/ACM Proc. Int. Workshop on Logic Synthesis, 1995, Lake Tahoe, NV.
    7. 7)
      • S. Juvekar , A. Taly , V. Kanade , S. Chakraborty . Efficient approximate symbolic reachability of discrete-timed digital circuits.
    8. 8)
      • Moon, I.-H.: `Efficient reachability algorithms in symbolic model checking', 2000, PhD, , Boulder, CO, USA, director-Somenzi, Fabio.
    9. 9)
      • Cabodi, G., Camurati, P., Quer, S.: `Symbolic exploration of large circuits with enhanced forward/backward traversals', EURO-DAC ’94: Proc. Conf. on European Design Automation, 1994, Los Alamitos, CA, USA, p. 22–27.
    10. 10)
      • Case, M.: `On invariants to characterize the state space for sequential logic synthesis and formal verification', April 2009, PhD, University of California, EECS Department, Berkeley, [online]. Available at: http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-46.html.
    11. 11)
    12. 12)
    13. 13)
      • Reda, S., Wahba, A.M., Salem, A.M., Borrione, D., Ghonaimy, M.: `On the use of don't cares during symbolic reachability analysis', ISCAS, 2001, 5, p. 121–124.
    14. 14)
      • Stoffel, D., Kunz, W.: `Record and play: a structural fixed point iteration for sequential circuit verification', Computer-Aided Design, 1997. 1997 IEEE/ACM Int. Conf. on Digest of Technical Papers, November 1997, p. 394–399.
    15. 15)
      • Coudert, O., Madre, J.C.: `A unified framework for the formal verification of sequential circuits', ICCAD, 1990, p. 126–129.
    16. 16)
      • Coudert, O., Madre, J.C., Berthet, C.: `Verifying temporal properties of sequential machines without building their state diagrams', CAV ’90: Proc. Second Int. Workshop on Computer Aided Verification, 1991, London, UK, p. 23–32.
    17. 17)
      • Bjesse, P., Claessen, K.: `Sat-based verification without state space traversal', Proc. Third Int. Conf. on Formal Methods in Computer-Aided Design, ser. FMCAD ’00, 2000, London, UK, p. 372–389, Available at: http://portal.acm.org/citation.cfm?id=646186.683097.
    18. 18)
    19. 19)
      • Shiple, T.R., Hojati, R., Sangiovanni-Vincentelli, A.L., Brayton, R.K.: `Heuristic minimization of BDDs using don't cares', DAC ’94: Proc. 31st Annual Conf. on Design Automation, 1994, New York, NY, USA, p. 225–231.
    20. 20)
      • Baumgartner, J., Kuehlmann, A., Abraham, J.A.: `Property checking via structural analysis', CAV, 2002, p. 151–165.
    21. 21)
      • Hong, Y., Beerel, P.A., Burch, J.R., McMillan, K.L.: `Safe BDD minimization using don't cares', Proc. 34th Annual Conf. Design Automation, DAC ’97, 1997, New York, NY, USA, p. 208–213.
    22. 22)
      • ‘Iscas’89 benchmarks’, http://www.cs.ubc.ca/spider/ajh/courses/cpsc538d/ ISCAS89/.
    23. 23)
      • S. Juvekar , A. Taly , V. Kanade , S. Chakraborty , S. Ramesh , P. Sampath . (2007) Approximate symbolic reachability of networks of transition systems, Next generation design and verification methodologies for distributed embedded control systems.
    24. 24)
    25. 25)
      • Baumgartner, J.R.: `Automatic structural abstraction techniques for enhanced verification', 2002, PhD, , supervisor: Jacob Abraham.
    26. 26)
    27. 27)
      • Burch, J.R., Clarke, E.M., McMillan, K.L., Dill, D.L., Hwang, L.J.: `Symbolic model checking: 1020 states and beyond', Proc. Fifth Annual IEEE Symp. on Logic in Computer Science (LICS 1990), June 1990, p. 428–439.
    28. 28)
      • ‘Berkeley logic synthesis and verification group, abc: a system for sequential synthesis and verification’, http://www.eecs.berkeley.edu/alanmi/abc/.
    29. 29)
      • Moon, I.-H., Hachtel, G.D., Somenzi, F.: `Border-block triangular form and conjunction schedule in image computation', FMCAD ‘00: Proc. Third Int. Conf. on Formal Methods in Computer-Aided Design, 2000, London, UK, p. 73–90.
    30. 30)
      • Abed, S., Mohamed, O.A., Al Sammane, G.: `Reachability analysis using multiway decision graphs in the HOL theorem prover', SAC ’08: Proc. 2008 ACM Symp. on Applied Computing, 2008, New York, NY, USA, p. 333–338.
    31. 31)
      • Burch, J.R., Clarke, E.M., Long, D.E.: `Representing circuits more efficiently in symbolic model checking', DAC ’91: Proc. 28th Conf. on ACM/IEEE Design Automation, 1991, New York, NY, USA, p. 403–407.
    32. 32)
      • ‘Hwmcc’08 benchmarks’, http://fmv.jku.at/hwmcc08/benchmarks.html.
    33. 33)
      • Edelkamp, S., Kissmann, P.: `Limits and possibilities of BDDs in state space search', KI ’08: Proc. 31st Annual German Conf. on Advances in Artificial Intelligence, 2008, Berlin, Heidelberg, p. 46–53.
    34. 34)
      • ‘Itc’99 benchmarks’, http://www.cad.polito.it/tools/itc99.html.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0048
Loading

Related content

content/journals/10.1049/iet-cdt.2010.0048
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address