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Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

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  • Author(s): S. Wang 1 ; J. Hu 2 ; S.G. Ziavras 3
    • View affiliations
    • Affiliations: 1: National Key Laboratory for Novel Software Technology, Nanjing University, Nanjing, People's Republic of China
      2: National Key Laboratory for Novel Software Technology, Intel Corporation, Portland, USA
      3: Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, USA
  • Source: Volume 6, Issue 1, January 2012, p. 50 – 58
    DOI:  10.1049/iet-cdt.2010.0102 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Published

Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar and simultaneous multi-threading (SMT) processors for instruction-level parallelism and thread-level parallelism exploitation. However, the large BTB not only dominates the predictor energy consumption, but also becomes a major roadblock in achieving faster clock frequencies at deep sub-micron technologies. The authors propose here a filtering scheme to dramatically reduce the accesses to the BTB to achieve significantly reduced energy consumption in the BTB while maintaining the performance. For a simulated superscalar microprocessor, the experimental evaluation shows that the BTB access filtering (BAF) design achieves an 88.5% dynamic energy reduction with negligible performance loss. The authors also study the leakage behaviour and its control in the BAF design. The results show that by applying a drowsy strategy, very effective leakage control can be achieved. For the high-performance design, the BAF can also improve BTB's performance scalability at new technologies. For the simultaneous multi-threading environment, the authors evaluate the effectiveness of the BAF design and propose a banked BAF (BK-BAF) scheme to further reduce the energy consumption and performance overhead. The experimental results confirm that the BK-BAF scheme can be an energy/performance-effective design for next generation SMT processors.

Inspec keywords: multiprocessing systems; energy consumption; clocks; multi-threading; channel bank filters; parallel architectures

Other keywords: high-performance microarchitectures; banked BAF scheme; dynamic energy reduction; low-energy microarchitectures; thread-level parallelism exploitation; simulated superscalar microprocessor; instruction-level parallelism; energy consumption; BTB access filtering design; deep sub-micron technologies; filtering scheme; branch target buffer access filtering; simultaneous multi-threading processors

Subjects: Multiprocessing systems; Digital signal processing; Filtering methods in signal processing; Parallel architecture

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