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Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

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Published

Partial reconfiguration suffers from low performance and thus its use is limited when the reconfiguration overhead is too high compared to the task execution time. To overcome this issue, the authors present a fast internal configuration access port (ICAP) controller, FaRM, providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as master accesses, ICAP overclocking, bitstream pre-load into a controller and bitstream compression technique, Offset-run length encoding (RLE), which is an improvement of the RLE algorithm. Combining these approaches allows us to achieve an ICAP theoretical throughput of 800 MB/S at 200 MHz. In order to complete our approach, we provide a cost model for the reconfiguration overhead for the system level that can be used during the early stages of development. The authors tested their approach on an Advanced Encryption Standard (AES) encryption/decryption architecture.

Inspec keywords: field programmable gate arrays

Other keywords: ICAP; internal configuration access port; reduction model; easy-to-use readback capabilities; high speed configuration; RLE; AES; advanced encryption standard; run length encoding; partial reconfiguration; cost model; bitstream compression technique; field programmable gate arrays

Subjects: Logic and switching circuits; Logic circuits

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