Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Design and evaluation of a high throughput robust router for network-on-chip

Design and evaluation of a high throughput robust router for network-on-chip

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.

Inspec keywords: telecommunication network routing; fault tolerance; network-on-chip

Other keywords: fault tolerant router design; deadlock freedom; router components; network links; deep submicron technology; multiple processors; running-time vulnerability; virtual channels; network-on-chip systems; adaptive routing algorithm; high-performance computing; high throughput robust router; manufacture defects; NoC systems

Subjects: Network-on-chip; Network-on-chip; Communication network design, planning and routing

References

    1. 1)
      • Fick, D., DeOrio, A., Chen, G., Bertacco, V., Sylvester, D., Blaauw, D.: `A highly resilient routing algorithm for fault-tolerant NoCs', Proc. Conf. on Design, Automation and Test in Europe, DATE '09, European Design and Automation Association, 3001 Leuven, 2009, Belgium, p. 21–26.
    2. 2)
    3. 3)
      • Rodrigo, S., Flich, J., Roca, A.: `Addressing manufacturing challenges with cost-efficient fault tolerant routing', Proc. 2010 Fourth ACM/IEEE Int. Symp. on Networks-on-Chip, NOCS’10, IEEE Computer Society, 2010, Washington, DC, USA, p. 25–32.
    4. 4)
      • R. Ubar , J. Raik , A. Jantsch , H. Tenhunen . (2004) Testing strategies for networks on chip, Networks on chip.
    5. 5)
      • Zhang, A., Greiner, A., Taktak, A.: `A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip', Proc. 45th Annual Design Automation Conf., DAC’08, ACM, 2008, New York, NY, USA, p. 441–446.
    6. 6)
    7. 7)
      • Valinataj, M., Mohammadi, S., Safari, S., Plosila, J.: `A link failure aware routing algorithm for networks-on-chip in nano technologies', Nineth IEEE Conf. on Nanotechnology, 2009, p. 687–690.
    8. 8)
    9. 9)
      • Lehtonen, L., Liljeberg, P., Plosila, J.: `Analysis of forward error correction methods for nanoscale networks-on-chip', Proc. Second Int. Conf. on Nano-Networks, Nano-Net’07, ICST, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2007, Brussels, Belgium, Belgium, 3, p. 1–3:5.
    10. 10)
    11. 11)
      • Pereira Frantz, A., Carro, L., Cota, E., Lima Kastensmidt, F.: `Evaluating SEU and crosstalk effects in network-on-chip routers', IEEE Int. On-line Testing Symp., 2006, p. 191–192.
    12. 12)
      • Eun Lee, S., Bagherzadeh, N.: `Increasing the throughput of an adaptive router in network-on-chip (NoC)', Proc. Fourth Int. Conf. on Hardware/Software Codesign and System Synthesis, CODES+ISSS '06, ACM, 2006, New York, NY, USA, p. 82–87.
    13. 13)
      • Yu, Q., Ampadu, P.: `Adaptive error control for NoC switch-to-switch links in a variable noise environment', IEEE Int. Symp. on Defect and Fault Tolerance of VLSI Systems, 2008, p. 352–360.
    14. 14)
      • Ali, M., Welzl, M., Hessler, S.: `A fault tolerant mechanism for handling permanent and transient failures in a network on chip', Fourth Int. Conf. on Information Technology, 2007, p. 1027–1032.
    15. 15)
    16. 16)
      • Pratim Pande, P., Ganguly, A., Feero, B., Belzer, B., Grecu, C.: `Design of low power reliable networks on chip through joint crosstalk avoidance and forward error correction coding', Twenty-first IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 2006, p. 466–476.
    17. 17)
      • Gilabert, F., Medardoni, S., Bertozzi, D.: `Exploring high-dimensional topologies for NoC design through an integrated analysis and synthesis framework', Int. Symp. on Networks-on-Chip, 2008, p. 107–116.
    18. 18)
      • Koibuchi, M., Matsutani, H., Amano, H., Mark Pinkston, T.: `A lightweight fault-tolerant mechanism for network on-chip', Proc. Second ACM/IEEE Int. Symp. on Networks-on-Chip, NOCS '08, IEEE Computer Society, 2008, Washington, DC, USA, p. 13–22.
    19. 19)
      • Park, D., Nicopoulos, C., Kim, J., Vijaykrishnan, N., Das, C.R.: `Exploring fault-tolerant network-on-chip architectures', Int. Conf. on Dependable Systems and Networks 2006, p. 93–104.
    20. 20)
      • Salihundam, P., Jain, S., Jacob, T.: `A 2tb/s 6′ 4 mesh network with DVFS and 2.3tb/s/w router in 45 nm CMOS', 2010 IEEE Symp. on VLSI Circuits (VLSIC), June 2010, p. 79–80.
    21. 21)
      • Wang, C., Hu, W.-H., Bagherzadeh, N.: `Congestion-aware network-on-chip router architecture', Fifteenth CSI Int. Symp. on Computer Architecture and Digital Systems (CADS), 2010, September 2010, p. 137–144.
    22. 22)
    23. 23)
      • Grecu, C., Pande, P., Ivanov, A., Saleh, R.: `Bist for network-on-chip interconnect infrastructures', Proc. 24th IEEE VLSI Test Symp., 2006.
    24. 24)
      • Schonwald, T., Zimmermann, J., Bringmann, O., Rosenstiel, W.: `Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures', Tenth Euromicro Conf. on Digital System Design Architectures, Methods and Tools, 2007, p. 527–534.
    25. 25)
      • Chaix, F., Avresky, D., Zergainoh, N., Nicolaidis, M.: `Fault-tolerant deadlock-free adaptive routing for any set of link and node failures in multi-cores systems', Nineth IEEE Int. Symp. on Network Computing and Applications (NCA), July 2010, p. 52–59.
    26. 26)
      • Zhou, J., Lau, F.C.M.: `Adaptive fault-tolerant wormhole routing in 2D meshes', Parallel and Distributed Processing Symp., Proc. 15th Int., April 2001, p. 8.
    27. 27)
      • Ho Bahn, J., Eun Lee, S., Bagherzadeh, N.: `On design and analysis of a feasible network-on-chip (NOC) architecture', ITNG ’07: Proc. Int. Conf. on Information Technology, IEEE Computer Society, 2007, Washington, DC, USA, p. 1033–1038.
    28. 28)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2011.0082
Loading

Related content

content/journals/10.1049/iet-cdt.2011.0082
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address