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Specification of interfering programs based on interconditions

Specification of interfering programs based on interconditions

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© The Institution of Electrical Engineers
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Flat VVSL is an extension of a VDM specification language wherein operations, which interfere through a shared state, can be specified in a VDM-like style by the use of interconditions in addition to pre-and postconditions. Interconditions are temporal formulae. In this paper, we explain the role of interconditions in the specification of interfering operations and describe the temporal formulae that can be used. We also describe the interpretation of operation definitions and temporal formulae in an infinitaiy logic of partial functions called MPIω. The purpose of this is to show how a VDM specification language is semantically combined with a temporal language. An overview of MPIω and the VVSL-specific aspects of its use for logical semantics is also provided.

Inspec keywords: formal logic; specification languages; formal specification

Other keywords: interfering programs; temporal formulae; partial functions; flat VVSL; interconditions; infinitary logic; operation definitions; temporal language; logical semantics; MPIω; interfering operations; VDM specification language

Subjects: Software engineering techniques; Formal logic; High level languages

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