A testability measure to improve algebraic test generation
A testability measure to improve algebraic test generation
- Author(s): Antonio Lioy and Marco Mezzalama
- DOI: 10.1049/sm.1984.0013
For access to this article, please select a purchase option:
Buy article PDF
Buy Knowledge Pack
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
Thank you
Your recommendation has been sent to your librarian.
- Author(s): Antonio Lioy 1 and Marco Mezzalama 1
-
-
View affiliations
-
Affiliations:
1: Dipartimento di Automatica e Informatica, CAD Group, Politecnico di Torino, Torino, Italy
-
Affiliations:
1: Dipartimento di Automatica e Informatica, CAD Group, Politecnico di Torino, Torino, Italy
- Source:
Volume 3, Issue 2,
April 1984,
p.
37 – 41
DOI: 10.1049/sm.1984.0013 , Print ISSN 0261-3182, Online ISSN 2053-9096
The paper deals with testability measures of digital systems. Specifically, a new algorithm to evaluate testability measures for circuits described in terms of Boolean equations is presented, and its application to speed up (algebraic) test generation for sequential networks is discussed.
Inspec keywords: field effect integrated circuits; integrated circuit testing; fault location; large scale integration
Other keywords:
Subjects: Other field effect integrated circuits; Electronic engineering computing
References
-
-
1)
- Fong, J.Y.: `On functional controllability and observability analysis', Proceedings of test conference, 1982, p. 170–175.
-
2)
- J.J. Thomas . Automated diagnostic test programs for digital networks. Comput. Des. , 63 - 67
-
3)
- Eichelberg, E.G., Williams, T.W.: `A logic design structure for LSI testing', Proceedings of 14th design automation conference, June 1977, p. 462–468.
-
4)
- Grason, J.: `TMEAS, a testability measurement program', Proceedings of 16th ieee design automation conference, 1979, p. 156–161.
-
5)
- Agrawal, V.D., Mercer, M.R..: `Testability measures — what do they tell us?', Proceedings of ieee test conference, 1982, p. 391–396.
-
6)
- B. Courtois . (1981) VLSI ‘81’, Failure mechanisms, fault hypotheses and analytical testing of LSI-NMOS (HMOS) circuits.
-
7)
- Goldstein, L.H., Thigpen, E.L.: `SCOAP: Sandia controllability/observability analysis program', Proceedings of 17th design automation conference, June 1980, p. 190–196.
-
8)
- Koenemann, B., Mucha, J., Zwiehoff, G.: `Built-in logic black observation technique', Digest of test conference, October 1979, p. 37–41.
-
9)
- Kovijanic, P.G.: `Testability analysis', Digest of ieee semiconductor test conference, October 1979, p. 310–316.
-
10)
- R.G. Bennetts , C.M. Maunder , G.D. Robinson . CAMELOT: a computer-aided meausre for logic testability. IEE Proc. E, Comput. & Digital Tech. , 5 , 177 - 189
-
11)
- T.W. Williams , K.P. Parker . Design for testability—a survey. IEEE Trans. , 2 - 15
-
12)
- Berg, W.C., Hess, R.D.: `COMET: a testability analysis and design modification package', Proceedings of ieee test conference, 1982, p. 364–378.
-
13)
- Breuer, M.A., Friedman, A.D.: `TEST/80, a proposal for an advanced automatic test generation system', Proceedings of ieee autotestcon, 1979, p. 305–312.
-
14)
- F.J. Hill , B. Huey . A design language based approach to test sequence generation. Computer , 28 - 33
-
15)
- L.H. Goldstein . Controllability/observability analysis of digital circuits. IEEE Trans. , 685 - 693
-
16)
- S. Gai , M. Mezzalama , P. Prinetto . A review of fault models for LSI/VLSI devices. Software & Microsyst. , 2 , 44 - 53
-
17)
- H.J. Nadig . Signature analysis — concepts, examples and guidelines. Hewlett-Packard J. , 15 - 21
-
1)