IEICE Trans - Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation

Jung-Yeol OH
Myoung-Seob LIM

Publication
IEICE TRANSACTIONS on Communications Vol.E89-B No.4 pp.1425-1429
Publication Date: 2006/04/01
Online ISSN: 1745-1345
DOI: 10.1093/ietcom/e89-b.4.1425
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Devices/Circuits for Communications
Keyword:
FFT, radix-2⁴, radix-2², SDF, CSD, multiplier,

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Summary:
This paper proposes the new radix-2⁴ FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2² algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.