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Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories
Kiyohiro FURUTANI Takeshi HAMAMOTO Takeo MIKI Masaya NAKANO Takashi KONO Shigeru KIKUDA Yasuhiro KONISHI Tsutomu YOSHIHARA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E88-C
No.2
pp.255-263 Publication Date: 2005/02/01 Online ISSN:
DOI: 10.1093/ietele/e88-c.2.255 Print ISSN: 0916-8516 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: DRAM, redundancy, high speed, high density,
Full Text: PDF(3.1MB)>>
Summary:
This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.
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