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An Energy-Efficient Clustered Superscalar Processor
Toshinori SATO Akihiro CHIYONOBU
Publication
IEICE TRANSACTIONS on Electronics
Vol.E88-C
No.4
pp.544-551 Publication Date: 2005/04/01 Online ISSN:
DOI: 10.1093/ietele/e88-c.4.544 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: low power architecture, energy reduction, clustered processors, dual-voltage pipeline, critical path prediction,
Full Text: PDF(538.7KB)>>
Summary:
Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.
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