IEICE Trans - An Exact Leading Non-Zero Detector for a Floating-Point Unit

An Exact Leading Non-Zero Detector for a Floating-Point Unit

Fumio ARAKAWA
Tomoichi HAYASHI
Masakazu NISHIBORI

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.570-575
Publication Date: 2005/04/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.4.570
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword:
floating-point, leading non-zero, normalize, embedded processor,

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Summary:
Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.