64-Bit High-Performance Power-Aware Conditional Carry Adder Design

Kuo-Hsing CHENG
Shun-Wen CHENG

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.6    pp.1322-1331
Publication Date: 2005/06/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.6.1322
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
conditional sum adder,  conditional carry adder,  power-aware,  hybrid dual-threshold voltage,  CMOS design,  

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Summary: 
The conditional sum adder (CSA) has been shown to outperform other adders applied in high-speed applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Based on the proposed adder architecture, six 64-bit hybrid dual-threshold CCAs for power-aware applications were discussed. Architectural modification of the CCA raises the operation speed, decreases the power dissipation, and lowers the hardware overhead. The proposed 64-bit CCA can decrease the number of multiplexers and internal nodes in the adder design by around 27% compared to the 64-bit CSA. Furthermore, components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.