IEICE Trans - A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique

A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique

Kang-Yoon LEE

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.9 pp.1900-1902
Publication Date: 2005/09/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.9.1900
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
Keyword:
delay-locked loop, multi-phase, frequency detection, jitter,

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Summary:
This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.