IEICE Trans - Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Noriaki ODA
Hiroyuki KUNISHIMA
Takashi KYOUNO
Kazuhiro TAKEDA
Tomoaki TANAKA
Toshiyuki TAKEWAKI
Masahiro IKEDA

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1544-1550
Publication Date: 2006/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.11.1544
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category:
Keyword:
copper, CMOS, damascene, design,

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Summary:
A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.