|
For Full-Text PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
|
Return Address Protection on Cache Memories
Koji INOUE
Publication
IEICE TRANSACTIONS on Electronics
Vol.E89-C
No.12
pp.1937-1947 Publication Date: 2006/12/01 Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.12.1937 Print ISSN: 0916-8516 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: low energy, security, cache, buffer overflow, stack smashing,
Full Text: PDF(1.6MB)>>
Summary:
The present paper proposes a novel cache architecture, called SCache, to detect buffer overflow attacks at run time. In addition, we evaluate the energy-security efficiency of the proposed architecture. On a return-address store, SCache generates one or more copies of the return address value and saves them as read only in the cache area. The number of copies generated strongly affects both energy consumption and vulnerability. When the return address is loaded (or popped), the cache compares the value loaded from the memory stack with the corresponding copy existing in the cache. If they are not the same, then return-address corruption has occurred. In the present study, the proposed approach is shown to protect more than 99.5% of return-address loads from the threat of buffer overflow attacks, while increasing the total cache-energy consumption by, at worst, approximately 23%, compared to a well-known low-power cache. Furthermore, we explore the tradeoff between energy consumption and security, and our experimental results show that an energy-aware SCache model provides relatively higher security with only a 10% increase in energy consumption.
|
|
|