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VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO Publication IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.230-242 Publication Date: 2006/03/01 Online ISSN: 1745-1353 DOI: 10.1093/ietele/e89-c.3.230 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: System LSIs and Microprocessors Keyword: optical flow, processor architecture, video segmentation, Full Text: PDF(4.2MB)>>
Summary: An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02  5.33 mm2 with six-metal 90-nm CMOS technology. | |||||
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