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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA Publication IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.250-262 Publication Date: 2006/03/01 Online ISSN: 1745-1353 DOI: 10.1093/ietele/e89-c.3.250 Print ISSN: 0916-8516 Type of Manuscript: Special Section INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Keyword: low power, CMOS, SoC, 90 nm, low voltage, variability, Full Text: PDF(2.1MB)>>
Summary: Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V. | |||||
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