IEICE Trans - A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

Ching-Yuan YANG
Jung-Mao LIN

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.1 pp.196-200
Publication Date: 2007/01/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.1.196
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword:
burst-mode CDR, clock recovery, phase-locked loop, realigned oscillation,

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Summary:
In this letter, a 1.25-Gb/s 0.18-µm CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4

1.4 mm², and power consumption is 32 mW under a 1.8-V supply voltage.