Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI

Satoshi SHIGEMATSU
Hiroki MORIMURA
Toshishige SHIMAMURA
Takahiro HATANO
Namiko IKEDA
Yukio OKAZAKI
Katsuyuki MACHIDA
Mamoru NAKANISHI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.10    pp.1892-1899
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.1892
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
test,  pixel parallel,  sensor,  fingerprint identification,  single chip,  high-functional device,  MEMS,  

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Summary: 
This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.