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Parasitic Effects in Multi-Gate MOSFETs Yusuke KOBAYASHI C. Raghunathan MANOJ Kazuo TSUTSUI Venkanarayan HARIHARAN Kuniyuki KAKUSHIMA V. Ramgopal RAO Parhat AHMET Hiroshi IWAI Publication IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.2051-2056 Publication Date: 2007/10/01 Online ISSN: 1745-1353 DOI: 10.1093/ietele/e90-c.10.2051 Print ISSN: 0916-8516 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: multi-gate, Fin-FETs, high-K dielectric, fringe capacitance, parasitic effect, Full Text: PDF(462.3KB)>>
Summary: In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations. | |||||
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