InP HEMT Technology for High-Speed Logic and Communications

Tetsuya SUEMITSU
Masami TOKUMITSU

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.5    pp.917-922
Publication Date: 2007/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.5.917
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Compound Semiconductor and Power Devices
Keyword: 
HEMT,  InP,  cutoff frequency,  OEIC,  

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Summary: 
As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.