The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time

Masaya MIYAHARA
Akira MATSUZAWA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.6    pp.1165-1171
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1165
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
analog to digital converter,  pipeline operation,  switched capacitor amplifier,  on resistance,  

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Summary: 
In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.