Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Jang Gn YUN; Il Han PARK; Seongjae CHO; Jung Hoon LEE; Doo-Hyun KIM; Gil Sung LEE; Yoon KIM; Jong Duk LEE; Byung-Gook PARK

doi:10.1093/ietele/e91-c.5.742

Special Section on Fundamentals and Applications of Advanced Semiconductor Devices

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Jang Gn YUN, Il Han PARK, Seongjae CHO, Jung Hoon LEE, Doo-Hyun KIM, Gil Sung LEE, Yoon KIM, Jong Duk LEE, Byung-Gook PARK

Author information

Jang Gn YUN
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Il Han PARK
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Seongjae CHO
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
The Institute of Electronics, Information and Communication Engineers
Jung Hoon LEE
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Doo-Hyun KIM
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Gil Sung LEE
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Yoon KIM
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Jong Duk LEE
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Byung-Gook PARK
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University

Keywords: 2-bit recessed channel memory, lifted-charge trapping node (L-CTN) scheme, short channel effect (SCE), second bit effect (SBE), bottom-side effect (BSE), V_TH window

JOURNAL RESTRICTED ACCESS

2008 Volume E91.C Issue 5 Pages 742-746

DOI https://doi.org/10.1093/ietele/e91-c.5.742

Details

Abstract

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (M_eff), is extended by lifting up them. The dependence of V_TH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (L_eff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

Corresponding author

Register with J-STAGE for free!