Special Section on Analog Circuits and Related SoC Integration Technologies
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
2008 Volume E91.C Issue 6 Pages 887-893
Details
2008 Volume E91.C Issue 6 Pages 887-893
For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90dB with low power. The measured SNR of the 100-MSPS ADC is 66.7dB at 1.2-V supply. Under that condition, each ADC dissipates only 55mW.
